Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be improved as the transistor size decreases.
A Fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while increasing transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin or on both vertical sidewalls and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FinFETs provide a promising candidate for small line width technology (e.g., approximately 22 nm and below) because of their excellent short channel effect control and scalability. Epitaxially-grown source and drain regions are often formed for the FinFETs by replacing portions of the fin with epitaxially-grown material. The epitaxially-grown source and drain regions may be employed to provide either compressive or tensile strain (depending upon whether a P-type FinFET or N-type FinFET is to be formed) within a channel of the FinFETs. The channel is the region of the fin disposed under a gate electrode structure and between the source region and the drain region. Compressive strain and tensile strain serve to increase hole mobility or electron mobility, respectively, within the channel. For example, the epitaxially-grown source and drain regions may include silicon germanium (SiGe) to provide compressive strain within the channel, thereby resulting in enhanced hole mobility that is desirable for P-type FinFETs. As another example, the epitaxially-grown source and drain regions may include silicon carbon (SiC) or/and silicon carbon phosphorous (SiC:P) to provide tensile strain within the channel, thereby resulting in enhanced electron mobility that is desirable for N-type FinFETs.
To form the epitaxially-grown source and drain regions, portions of the fin adjacent to the gate electrode structure are etched to form trenches, followed by epitaxially growing the appropriate material (depending upon whether P-type FinFETs or N-type FinFETs are to be formed) in the trenches. To selectively expose portions of the fin where trenches are to be formed, a hard mask is patterned to define gaps where the trenches are to be formed. Sidewall spacers formed from material of the hardmask remain disposed adjacent to the fin after patterning and after formation of the trenches. Epitaxial growth generally propagates both vertically and laterally, with the epitaxially-grown material growing over the sidewall spacers and toward epitaxially-grown source and drain regions of adjacent fins, often resulting in merger of the epitaxially-grown source and drain regions of adjacent fins. Merger of the epitaxially-grown source and drain regions of adjacent fins will result in failure for single fin devices (where multiple adjacent fins each include separate transistors). Avoiding merger of epitaxially-grown source and drain regions of adjacent fins becomes more difficult as line width technology continues to scale down, with distances between fins becoming smaller and smaller. Further, efforts to minimize a profile of the epitaxially-grown source and drain regions results in less available surface area of the epitaxially-grown source and drain regions for formation of silicide, thereby possibly compromising effective electrical connection to the epitaxially-grown source and drain regions especially as line width technology continues to scale down.
Accordingly, it is desirable to provide FinFET devices and methods of forming such FinFET devices that avoid merger between epitaxially-grown source and drain regions of adjacent fins while also maximizing available surface area of the epitaxially-grown source and drain regions for formation of silicide, even as line width technology continues to scale down. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.